A typical integrated circuit floorplan may have core logic circuitry formed in the center region of the integrated circuit and input-output circuitry (i.e., interface circuitry) formed along the periphery of the integrated circuit. However, such conventional floorplan designs exhibit drawbacks, one of which includes inefficient usage of corner regions.
Most integrated circuit dies are relatively large in order to accommodate a large core region. The interface circuitry, which generally occupies a relatively small floorplan area, occupies only a portion of the corner regions on the integrated circuit. Therefore, the corner regions on the integrated circuit may not be fully utilized.
In addition to that, such floorplans may not be optimal for designs with strict timing requirements. For example, there may be a significant distance between an input-output circuit located at a corner of the peripheral region and the corresponding logic resource in the core region. The large distance between the two circuits can result in timing violations as critical timing pathways may not be able to meet timing constraints (especially in memory interfacing applications).
Another known drawback with such floorplans is the resource contention between the input-output circuitry at the peripheral region and the logic circuitry at corners of the core region.